The present invention relates to a bit line voltage sensing circuit of a semiconductor memory device, and in particular, to a circuit capable of stably sensing the bit line voltage while minimizing power noise.
A dynamic random access memory (also referred to as a DRAM) is a well known memory device. Its memory cell consists of one transistor and one small capacity capacitor. A bit line sense amplifier, which conventionally includes a PMOS latch and an NMOS latch, is required for reading out data information stored in the capacitor. As access times increase, the time required for bit line sensing relative to other DRAM operations has increased. Upon sensing information, a peak current is generated on the bit line and flows as noise which may deteriorate the overall operation of the DRAM. Accordingly, methods for accelerating sensing speed while minimizing the peak current are desirable.
FIG. 1 is a circuit diagram illustrating the construction of a memory cell array of a semiconductor memory device and FIG. 4 is a wave form illustrating operational characteristics of each component of FIG. 1. The wave form of FIG. 4 shows a block select signal BLSiB, which designates an array block activated. In the state which precedes activation of the block select signal BLSiB, since an equalizing signal .phi.EQB 412 of FIG. 4 is in a logic "high" state, each of bit lines BL and BLB is precharged and equalized to a voltage VBL level by a precharge circuit 111 and an equalizing circuit 112. The voltage VBL represents an intermediate voltage level of a power supply voltage VCC.
Under the state mentioned above, when the block select signal BLSiB, is activated to a logic low state as shown in FIG. 4, the equalizing signal .phi.EQB 412 is changed to the logic low state and a selected memory block performs a bit line sensing operation. That is, once the equalizing circuit 112 is changed to the logic low state due to equalizing signal .phi.EQB 412 of FIG. 4, the equalizing circuit 112 electrically separates the bit lines BL and BLB. Thereafter, a word line enable signal WL 413 shown in FIG. 4 is generated with a voltage boosted to a level (VCC+.alpha.) higher than the power supply voltage Vcc. Accordingly, when the word line enable signal WL occurs, data information stored in a capacitor of a memory cell 113 is output to a bit line BL0 , and a charge sharing occurs between them. As a result, an electric potential difference .DELTA.VBL0 shown in FIG. 4 is generated between the bit lines BL and BLB by the data information stored in the memory cell 113 assuming that data having a high voltage "1" level has read-out.
The electric potential difference .DELTA.VBL0 between the bit lines BL and BLB must then be developed to the difference between the power supply voltage and a ground voltage, which is typically done using a P-sense amplifier 114 and an N-sense amplifier 116. Then, if sense activating signals .phi.S shown at 414 of FIG. 4 and .phi.SB shown at 415 of FIG. 4 are activated by the word line enable signal WL, a pull-down control signal LANG and a pull-up control signal LAPG are, respectively, activated as shown at 416 and 417 of FIG. 4. The construction of a pull-down control signal generator for generating the pull-down control signal LANG and the construction of a pull-up control signal generator for generating the pull-up control signal LAPG will be further described.
The pull-down control signal generator for controlling power supply LAB which enables N-sense amplifier 116 illustrated in FIG. 3 includes a NAND gate 312 and receives an output of inverter 311, which inverting the signal and BLSiB as shown by 411 of FIG. 4 and .phi.S as shown by 414 outputs a logic "low" signal when the signal .phi.S is changed to the logic "high" state so that the two signals are input in the logic "high" state, and thus generates the pull-down control signal LANG having a logic "high" state as shown by 416 of FIG. 4 using an inverter 313.
The pull-up control signal generator for controlling a power supply LA which enables the P-sense amplifier 114 and includes NOR gate 211 which receives the signals .phi.SB shown by 415 of FIG. 4 and BLSiB shown by 411 of FIG. 4 and outputs a logic high signal when the signal .phi.S is changed to the logic high state so that the two signals are input at a logic low level and the pull-up control signal LAPG having a logic low shown by 417 of FIG. 4 is thus generated using inverters 212 to 214. Therefore, when the pull-down control signal LANG shown by 416 of FIG. 4 is generated, pull-down transistor 122 of FIG. 1 is turned on, thereby supplying ground voltage to the N-sense amplifier 116.
When one of the NMOS transistors in the N sense amplifier 116 is initially turned on more than the other, its gate electrode is coupled to a bit line having a potential level VBL+.DELTA.VBL0 and the bit line having a logic "low" potential as shown by 421 of FIG. 4 is thereafter pulled-down to the ground voltage. Moreover, when the pull-up control signal LAPG as shown by 417 of FIG. 4 is generated, a pull-up transistor 121 of FIG. 1 is turned on, thereby supplying the power supply voltage Vcc to the P-sense amplifier 114. Thereafter, when one of the PMOS transistors in the P sense amplifier 114 is initially turned on more than the other, its gate electrode is coupled to a bit line having a potential level VBL-.beta. the bit line having the potential VBL+.DELTA.VBL0 level as shown by 420 of FIG. 4 is pulled-up to the power supply voltage. Thus, when the power supply LAB and LA are supplied, the bit lines BLB and BL initially having an electric potential difference of .DELTA.VBL0 are developed to the potential difference between the ground voltage and the power supply voltage.
The bit line sensing operation set forth above can be implemented using two methods. One method accelerates a slope of the pull-up control signal LAPG as shown in 417 of FIG. 4, which requires using a larger size inverter 214 of the pull-up control signal generator shown in FIG. 2. If the slope of the pull-up control signal LAPG is quickly changed, the speed of the sensing operation is advantageously high, and sufficient time for the restoring operation of the memory cells is obtained, since the pull-up transistor 121 has a good conductivity. However, since the control signal LAPG is quickly changed, a large peak current is generated on the pulled-up bit lines and line LA. This results in peak current problems and can have a detrimental influence on power supply operation, and serious power line noise capable of instantly causing malfunction of the memory device can be generated.
The other method of implementing the sensing operation slowly controls the slope of the pull-up control signal LAPG as shown by dotted line 427 of FIG. 4, which can be obtained by reducing the size of the inverter 214 of the pull-up control signal generator shown in FIG. 2. If the pull-up control signal LAPG is slowly varied, the peak current can be advantageously minimized, thereby eliminating the power line noise. However, this method results in slow bit line sensing speed and there is not, therefore, sufficient time for the restoring operation, thereby causing the .DELTA.VBL0 level to be smaller than desired in a next sensing operation.
Accordingly, an improved apparatus for implementing bit line sensing is needed.